1. Field of the Invention
The present invention relates to a semiconductor memory device including a bit line load circuit or equalizing circuit (equalizer), and, in particular, to a semiconductor memory device of a high speed read-out operation, and the like.
2. Description of the Prior Art
Conventionally, the technology for this type of field is as illustrated, for example, in FIG. 1.
FIG. 1 is a main configuration diagram showing the configuration of a bit line peripheral circuit in a conventional static RAM (hereinafter referred to as an SRAM).
This SRAM is provided with a bit line pair BL, BLB and a plurality of word lines WL, arranged in a lattice form or a matrix form. The points of intersection are respectively connected to a memory cell 101.
Tile memory cell 101 comprises NMOSs 101a to 101d and resistances 101e and 101f, as shown in FIG. 2. A row decoder 102 for decoding row addresses (bit line direction addresses) is connected to the word lines WL.
The bit lines of the bit line pair BL, BLB are respectively connected to common data lines DL, DLB through transistor gates 103, 104.
The transfer gates 103, 104 operate for selecting column addresses, and controlling the ON and OFF states of these column addresses by means of a column signal CD transmitted from a column decoder 105 and an inverted column signal CDB which is the column signal CD inverted via an inverter 105a.
A bit line upper load circuit 106 is connected to the uppermost sections of the bit line pair BL, BLB. Also, a bit line lower load circuit 107 is connected to the common data lines DL, DLB through a common bit line pair CBL, CBLB. The bit line upper load circuit 106 comprises a plurality of P-MOSs 106a to 106e, and the bit line lower load circuit 107 comprises a plurality of P-MOSs 107a to 107c, as shown in FIG. 2.
A sense amplifier 108 for amplifying read data and transmitting this data to common read lines MS, MSB is connected to the bit line lower load circuit 107. The sense amplifier 108 comprises a pair of NPN transistors 108a, 108b and an N-MOS 108c, as shown in FIG. 2.
A section write enable generation circuit 109 is provided on this bit line peripheral circuit. The section write enable generation circuit 109 is a circuit for activating a write operation for the various sections when all the memory cells have been divided into a certain number of sections, and for transmitting a section write enable signal SWE and its inverted signal SWEB.
The section write enable signal SWE controls operations of the bit line upper load circuit 106 and the bit line lower load circuit 107. This signal changes to the low level for an unselected section or during a read operation, and acts so that the impedance of the bit line load is small, the impedance of the bit line load is large only when there is a selected section and a write, and the write operation is not influenced by the bit line load.
The inverted signal SWEB of the section write enable signal SWE is at the high level during a read out for a section selected from a section divided into several sections, and activates the sense amplifier 108. Data from the memory cell 101 is transmitted to the common read lines MS, MSB, is at the low level during a write-in or for a selected section, and inactivates the sense amplifier 108.
In addition, the write circuit 110 is connected to the common bit lines CBL, CBLB.
Next, the operation of the above-mentioned bit line peripheral circuit will be explained.
When the word line WL and the column line CD specified by the row address and the column address are activated by the row decoder 102 and the column decoder 105, the transfer gates 103, 104 are turned ON, and the memory cell 101 corresponding to the row address and the column address is selected.
During a read operation, the section write enable signal SWE and the inverted signal SWEB thereof are changed to the low level and the high level respectively. The impedance of the bit line upper load circuit 106 and that of the bit line lower load circuit 107 are reduced by the section write enable signal SWE. Also, the sense amplifier 108 is activated by the section write enable signal SWEB.
As a result, data which is "1" or "0" stored in the selected memory cell 101 is transmitted to the common read line MS via the bit line BL and the common bit line CBL. In the same manner, the inverted data read out from the memory cell 101 is transmitted to the common read line MSB via the bit line BLB and the common bit line CBLB.
During a write operation, the section write enable signal SWE is changed to the high level and the inverted signal SWEB thereof is changed to the low level. The impedance of the bit line upper load circuit 106 and that of the bit line lower load circuit 107 are increased by the section write enable signal SWE. Also, the sense amplifier 108 is inactivated by the section write enable signal SWEB.
As a result, when the write data is supplied to the bit line BL and the inverted write data is supplied to the bit line BLB by the write circuit 110, the data is stored in the memory cell 101.
FIG. 3 is a diagram showing the condition of a conventional bit line amplitude .DELTA.VBL corresponding to a bit line position.
Here, the bit line amplitude .DELTA.VBL can be represented as: EQU .DELTA.VBL=.DELTA.VBL-.DELTA.VBLB
where VBL is the voltage of the bit line BL and VBLB is the voltage of the bit line BLB.
Changes in the bit line amplitude .DELTA.VBL shown in the drawing are produced by the different row addresses accessed.
In the case where the memory cell 101 positioned on the upper section of the bit line pair BL, BLB is accessed, when the bit line BL and the bit line BLB are at the low level and the high level respectively, a current I1+i1 (I1&gt;i1) from the bit line upper load circuit 106 or a current I2+i2 (I2&gt;i2) from the bit line lower load circuit 107 flows into the memory cell 101, and a cell current Icell becomes Icell=I1+i1+I2+i2. In this case I1+i1&gt;&gt;I2+i2 and the bit line amplitude .DELTA.VBL can be illustrated as the solid line .DELTA.VBL1 in FIG. 3.
In the case where the memory cell 101 positioned on the lower section of the bit line pair BL, BLB is accessed, when the bit line BL and the bit line BLB are at the low level and the high level respectively, a current I1'+i1' (I1'&gt;i1') from the bit line upper load circuit 106 or a current I2'+i2' (I2'&gt;i2') from the bit line lower load circuit 107 flows into the memory cell 101 in the same manner, and a cell current Icell' becomes Icell'=I1'+i1'+I2'+i2'. In this case I1'+i1'&gt;I2'+i2' and I2&lt;&lt;I2' and i2&lt;i2', and, also, the bit line amplitude .DELTA.VBL can be illustrated as the solid line D VBL2 in FIG. 3.
In the case where the impedance of the bit line upper load circuit 106 is r0 and the impedance of the bit line lower load circuit 107 is r1, the relationship between the two impedances is r1&gt;&gt;r0. In addition, the bit line amplitude D VBL entering the sense amplifier 108 when the lower section of the memory cell 101 is accessed becomes r0(I2-i2) and when the lower section of the memory cell 101 is accessed becomes r1(I2'-i2'). The relationship is r0(I2-i2)&lt;r1(I2'-i2').
When the bit line resistance from the upper memory cell 101 to the bit line upper load circuit 106 is R1 and the bit line resistance from the upper memory cell 101 to the bit line lower load circuit 107 is R2, the maximum value of the bit line amplitude .DELTA.VBL1 can be represented as R2(I2+i2). Also, when the resistance of the bit line BLB from the lower memory cell 101 to the bit line upper load circuit 106 is R1 and the resistance of the bit line BLB from the lower memory cell 101 to the bit line lower load circuit 107 is R2, the maximum value of the bit line amplitude .DELTA.VBL2 can be represented as R2'(I2'+i2').
Next, as another example of a conventional bit line peripheral circuit, in the above-mentioned bit line peripheral circuit of FIG. 7, an explanation is given for the case where the bit line upper load circuit 106 only is omitted.
FIG. 4 is a diagram showing the condition of the bit line amplitude .DELTA.VBL corresponding to the bit line position in this case.
In the case where the memory cell 101 (upper memory cell) positioned in the upper section of the bit line pair BL, BLB is accessed, a cell current Icell=I3+i3 flows into the upper memory cell 101 from the bit line lower load circuit 107. In this case the bit line amplitude .DELTA.VBL can be represented as the solid line .DELTA.VBL3 in FIG. 4. On the other hand, in the case where the lower memory cell 101 positioned in the lower section of the bit line pair BL, BLB is accessed, the bit line amplitude .DELTA.VBL is added on the solid line .DELTA.VBL3 in FIG. 4, corresponding to the above-mentioned bit line position.
In this case, when the impedance of the bit line lower load circuit 107 is r2, the bit line amplitude .DELTA.VBL entering the sense amplifier 108, as clearly shown in FIG. 4, is not related to the bit line position of the accessed memory cell, but normally is equivalent to r2(I3-i3).
However, the following problem areas exist in the above-mentioned conventional semiconductor memory of the bit line load circuit type.
When the memory size (or volume) is small and the bit line length is short, as shown in FIG. 4, it is preferable to provide a bit line load circuit on the lower section only. This is because the bit line amplitude .DELTA.VBL transmitted to the sense amplifier 108 is normally set at r2(I3-i3), unrelated to the bit line position of the accessed memory cell. However, in the case where the memory size or memory volume is large and the bit line length is long, when the bit line load circuit is provided on the lower section only, the difference in the bit line amplitudes .DELTA.VBL on the bit line is large, and the inverted speed of the data on the bit line pair BL, BLB is rather retarded.
Accordingly, in the case where the bit line load circuit is provided on both the upper and lower sections, as shown in FIG. 3, the difference in the bit line amplitudes .DELTA.VBL on the accessed bit line is limited within a certain range, and the row address dependence of the inverted speed of the data on the bit line pair BL, BLB is small.
However, as outlined above, the bit line amplitude .DELTA.VBL transmitted to the sense amplifier 108 is r1(I2-i2) when the memory cell 101 of the upper section of the bit line is accessed, and is r1(I2'-i2') when the memory cell 101 of the lower section of the bit line is accessed, so there is still dependence on the row address.
As a result, there is the problem of wide variation in the access times of the addresses during read-out.
FIGS. 5A to 5C are characteristic diagrams for specifically explaining this point.
FIG. 5A is a diagram illustrating the dependence of the bit line delay on the bit line amplitude .DELTA.VBL.
FIG. 5B is a diagram illustrating the dependence of the sense amplifier delay on the bit line amplitude .DELTA.VBL.
FIG. 5C is a diagram illustrating the dependence of the read-out delay on the bit line amplitude .DELTA.VBL obtained from these characteristics.
As clearly shown in FIG. 5A, because the bit line delay increases as the bit line amplitude .DELTA.VBL increases, time is required for the data inversion. As clearly shown in FIG. 5B, because the sense amplifier delay decreases as the bit line amplitude .DELTA.VBL increases, the gain increases and the read-out operation is speeded up. Also, as clearly shown in FIG. 5C, if the bit line amplitude .DELTA.VBL becomes too small, the read-out delay resulting from the sense amplifier delay is increased, and if the bit line amplitude D VBL becomes too large, the read-out delay resulting from the bit line delay is also increased.
Accordingly, with the above-mentioned conventional bit line load circuit type of memory, in particular, in the case of a large size memory or large volume memory, the row address dependence of the bit line amplitude is large, and the variation in the access times of the addresses during read-out is great.